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Voltage Amplifier in Single-end Common-collector and Common-emitter Configuration and Bi-directional Zero Climax Compensation Network

A patent technology registered whit the State Intellectual property Office of P.R China.
Patentee:Yu Jianbing



    With laconic circuit and elegant and moving sound orientation, that psychoacoustics influences on subjective listening was fully considered when the circuit was designed and developed. Below is the main content on this electric circuit.

    Among kinds of audio transistor amplifier, the highest nonlinear distortion and harmonic distortion in amplification stage is voltage amplifier, so to improve this stage characteristic will be quite good for overall system behavior .In the light of this, the design for this circuit started with improving function of voltage amplifier.

    Generally, voltage amplifier in audio amp mostly uses common-emitter configuration. The transistor input characteristic shows that common-emitter configuration will generate interface distortion caused by increased input voltage and base current leading to bad output characteristic of collector and sharply reduced input impedance. All of these will also, in this stage, cause bad parameter of distortion and frequency response. A little better voltage amp mostly adopts common-emitter common-base configuration which can improve this stage’s function to some extent but common-emitter common-base circuit, on aspect of sound expression, can’t provide enough relaxing and natural sound, inclining to a little tight and lifeless sound feature which is kept to by the characteristic of common-emitter common-base circuit.

    Common-emitter common-base circuit has made greater contribution to improving high frequency response and distortion but in regard to low frequency it becomes bad due to higher internal impedance of electric circuitry. According to accumulated experiences and data from former experiment it demonstrates: If it is possible that voltage amp is driven by current signal source with low internal impedance, interface distortion could be improved in great measure. In the light of this “voltage amplifier in single-end common-collector and common-emitter configuration” was developed.

    Before common-emitter voltage amplifying transistor one common-collector amplifying stage (Q1) is added to exert current driving on common-emitter voltage amplifying transistor (Q2) so that it improves Q2’s input characteristic and reduces interface distortion, raises the voltage amp’s behavior when high output voltage swings

    In addition, why to have chosen single-end voltage amplifying instead of PP voltage amplifying, besides above causes, also has other reason-------- to make this stage’s distortion have such frequency spectrum characteristic that even-order harmonics is main volume. Experiments showed the creative idea for this circuit can be established and has attained design goal. Among total harmonic even harmonic is more than odd harmonic and distortion at high frequency (10KHz-20KHz) is lower than at mid-low-frequency. This is a rare example which is just reverse of distortion of general voltage amplifiers. Moreover the circuit characteristic is improved when high output voltage in voltage amplifier swings.

    Because it is a single-end voltage amplifier and this stage’s gain is a little lower temperature compensation constant-current source is specially installed to raise gain at this stage. Also as a single-end voltage amplifier with narrower open-loop frequency response, in order to ensure that systematic loop circuit feedback, within 20Hz to 20KHz, is negative feedback tow lead compensation networks (C2C3R4) are set up at this stage to compensate it for lack of open-loop frequency response, together with lag compensation network (R1C1 to compensate for closed loop characteristic) they form” bi-directional zero climax compensation network” Three networks feature 6d/oct with more ideal internal and external characteristic . Its frequency response at high frequency drops simply, smoothly and slowly without any peak-to-valley, approximating 1MHz. Rated power bandwidth is 620KHz(disconnecting low-pass network)

    During the design we used software, PSpic to exert emulative optimization on the circuitry

     
 
 

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